1. Field of the Invention
The present invention relates to a digital/analog (hereafter, "D/A") converter and in particular to a high speed resistor string D/A converter.
2. Background of the Related Art
FIG. 1 is a circuit diagram illustrating a related art D/A converter using a resistor string. The D/A converter includes a decoder 10 for decoding N-bit input data and outputting decoding signals 0.about.2.sup.N-1 and a resistor string 11 with a plurality 2.sup.N +1 resistors R coupled in series between a reference voltage Vref terminal and ground voltage Vss. A switching unit 12 has a plurality of switches SW1.about.SW2.sup.N for outputting voltages distributed at respective nodes 1.about.2.sup.N of the resistor string 11 to an output terminal Vout in accordance with the decoding signals 0.about.2.sup.N-1 from the decoder 10.
The operation of the related art D/A converter will now be described. The reference voltage Vref is distributed by the respective resistors R. Accordingly, the nodes 1.about.2.sup.N of the resistor string 11 maintain the distributed voltage values. When an N-bit input signal is applied, the decoder 10 decodes the N-bit signal and outputs the decoding signals 0.about.2.sup.N-1. The switching unit 12 may be turned on or off in accordance with the decoding signals 0.about.2.sup.N-1 outputted from the decoder 10. Therefore, the voltages at the nodes 1.about.2.sup.N are outputted through the turned-on switches SW1.about.SW2.sup.N to the output terminal Vout, to generate an analog voltage having levels of 0.about.2.sup.N.
A settling time Tc, which indicates a time to stabilize the output voltage to 1/2 LSB (least significant bit) in the D/A converter, is determined by a delay time Td of the decoder 10 and a time constant T of an RC circuit. The settling time Tc may be expressed by equation 1 as follows: EQU Tc=Td+(N+1).multidot.T.multidot.1n2 (1)
In equation 1, N is the number of bits.
FIG. 2 is an equivalent circuit of FIG. 1 for obtaining the time constant T of the RC circuit in equation 1. In FIG. 2, Veq and Req respectively denote an equivalent voltage and an equivalent resistance in the resistor string 11, and Ron and Cp respectively indicate a turn-on resistance and a parasitic capacitance of each of the respective switches SW1.about.SW2.sup.N. The time constant T in the equivalent circuit of FIG. 2 is approximately obtained by equation 2 as follows: EQU T=2.sup.N .multidot.Cp(Ron+Req)+Cp.multidot.Req (2)
If the value of the time constant T expressed in equation 2 is substituted for the time constant T in equation 1, the setting time Tc is obtained by equation 3 as follows: EQU Tc=Td+(N+1).multidot.1n2.multidot.[2.sup.N .multidot.Cp(Ron+Req)+Cp.multidot.Req] (3)
However, in the related art D/A converter, if an input bit number N is not less than six (N.gtoreq.6), the parasitic capacitance Cp of the output terminal Vout is increased, which increases the settling time Tc. That is, the increase of the bit number N in equation 3 satisfies Tc.apprxeq.2.sup.N .multidot.Cp.multidot.(Ron+Req)(N+1).multidot.1n2. At this time, assuming that the equivalent resistance Req of the resistor string 11 is sufficiently smaller than a turn-on resistance Ron of the switches SW1.about.SW2.sup.N, the setting time Tc may be approximately expressed by equation 4 as follows: EQU Tc.apprxeq.2.sup.N .multidot.Cp.multidot.Ron(N+1).multidot.1n2(4)
As described above, the related art D/A converter has various disadvantages. The D/A related art converter has a disadvantage in that the increase of a bit number N causes the settling time Tc to increase in proportion to 2.sup.N (N+1).
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.